1. Field of the Invention
The invention relates generally to the fabrication of semiconductor devices and to polishing and planarizing substrates.
2. Background of the Related Art
Reliably producing sub-half micron and smaller features is one of the key technologies for the next generation of very large scale integration (VLSI) and ultra large-scale integration (ULSI) of semiconductor devices. However, as the fringes of circuit technology are pressed, the shrinking dimensions of interconnects in VLSI and ULSI technology has placed additional demands on the processing capabilities. The multilevel interconnects that lie at the heart of this technology require precise processing of high aspect ratio features, such as vias, contacts, lines, and other interconnects. Reliable formation of these interconnects is important to VLSI and ULSI success and to the continued effort to increase circuit density and quality of individual substrates and die.
Multilevel interconnects are formed by the sequential deposition and removal of materials from the substrate surface to form features therein. As layers of materials are sequentially deposited and removed, the uppermost surface of the substrate may become non-planar across its surface and require planarization prior to further processing. Planarizing a surface, or xe2x80x9cpolishingxe2x80x9d a surface, is a process where material is removed from the surface of the substrate to form a generally even, planar surface. Planarization is useful in removing excess deposited material and removing undesired surface topography and surface defects, such as rough surfaces, agglomerated materials, crystal lattice damage, scratches, and contaminated layers or materials to provide an even surface for subsequent processing.
Chemical mechanical planarization, or chemical mechanical polishing (CMP), is a common technique used to planarize substrates. In conventional CMP techniques, a substrate carrier or polishing head is mounted on a carrier assembly and positioned in contact with a polishing media in a CMP apparatus. The carrier assembly provides a controllable pressure to the substrate urging the substrate against the polishing media. The substrate and polishing media are moved in a relative motion to one another.
A polishing composition is provided to the polishing media to effect chemical activity in removing material from the substrate surface. The polishing composition may contain abrasive material to enhance the mechanical activity between the substrate and polishing media. Thus, the CMP apparatus effects polishing or rubbing movement between the surface of the substrate and the polishing media while dispersing a polishing composition to effect both chemical activity and mechanical activity. The chemical and mechanical activity removes excess deposited materials as well as planarizing a substrate surface.
Chemical mechanical polishing may be used in the fabrication of shallow trench isolation (STI) structures. STI structures that may be used to separate transistors and components of a transistor, such as source/drain junctions or channel stops, on a substrate surface during fabrication. STI structures can be formed by depositing a series of dielectric materials and polishing the substrate surface to remove excess or undesired dielectric materials. An example of a STI structure includes depositing a silicon nitride layer on an oxide layer formed on a doped silicon substrate surface, patterning and etching the substrate surface to form a feature definition, depositing a silicon oxide fill of the feature definitions, and polishing the substrate surface to remove excess silicon oxide to form a feature. The silicon nitride layer may perform as a hard mask during etching of the features in the substrate and/or as a polishing stop during subsequent polishing processes. Such STI fabrication processes require polishing the silicon oxide layer to the silicon nitride layer with a minimal amount of silicon nitride removed during the polishing process in order to prevent damaging of the underlying materials, such as oxide and doped silicon.
The STI substrate is typically polished using a conventional polishing media and an abrasive containing polishing slurry. However, polishing STI substrates with conventional polishing media and abrasive containing polishing slurries has been observed to result in overpolishing of the substrate surface and form recesses in the STI features and other topographical defects such as microscratches on the substrate surface. This phenomenon of overpolishing and forming recesses in the STI features is referred to as dishing. Dishing is highly undesirable because dishing of substrate features may detrimentally affect device fabrication by causing failure of isolation of transistors and transistor components from one another resulting in short-circuits. Additionally, overpolishing of the substrate may also result in nitride loss and exposing the underlying silicon substrate to damage from polishing or chemical activity, which detrimentally affects device quality and performance.
One solution to limit dishing of substrate features is to polish a substrate surface with abrasive sheet polishing media. Abrasive sheet polishing media typically contains abrasive particles held in a containment media, which provide mechanical activity to the substrate surface along with the polishing media when contacting the substrate surface. However, abrasive sheet polishing media have been observed to excessively polish the underlying silicon nitride layer of STI substrates when polishing silicon oxide layers. The excessive nitride polishing results in nitride loss, exposing the underlying silicon substrate to damage from polishing or chemical activity, which detrimentally affects device quality and performance.
FIGS. 1A-1C are schematic diagrams illustrating the phenomena of dishing and nitride loss. FIG. 1A shows an example of one stage of the STI formation process with a silicon nitride layer 20 and thermal oxide layer 15 disposed and patterned on a substrate 10. A silicon oxide material 30 is deposited on the substrate surface in sufficient amounts to fill features 35.
FIG. 1B illustrates the phenomena of dishing observed with polishing by conventional techniques. During polishing of the silicon oxide material 30 to the silicon nitride layer 20, the silicon oxide material 30 may be overpolished and surface defects, such as recesses 40, may be formed in the silicon oxide material 30. The excess amount of silicon oxide material removed from overpolishing the substrate surface, represented by dashed lines, is considered the amount of dishing 50 of the feature.
FIG. 1C illustrates nitride loss from the surface of the silicon nitride layer 20 from excess polishing of the substrate surface with conventional polishing processes. Silicon nitride loss may take the form of excess removal of silicon nitride, or xe2x80x9cthinningxe2x80x9d of the silicon nitride layer, from the desired amount 60 of silicon nitride. The silicon nitride loss may render the silicon nitride layer 30 unable to prevent or limit damage to or contamination of the underlying substrate material during polishing or subsequent processing.
Therefore, there exists a need for a method and related polishing apparatus, which facilitates the removal of dielectric materials with minimal or reduced dishing and minimal or reduced loss of underlying materials.
The invention generally provides a method and composition for planarizing a substrate surface with selective removal rates and low dishing. In one aspect, the invention provides a method of processing a substrate including contacting a substrate having at least first and second dielectric materials disposed thereon with a polishing platen having polishing media disposed thereon, providing an abrasive free polishing composition comprising one or more surfactants to the substrate, and removing the first dielectric material at a higher removal rate than the second dielectric material.
In another aspect, the invention provides a method of processing a substrate, including providing a substrate having an oxide material disposed on a nitride material disposed thereon to a polishing platen having polishing media disposed thereon, providing a polishing composition consisting essentially of one or more surfactants, one or more pH adjusting agents, and deionized water, to a substrate surface, forming a removal resistant surface on the nitride material, and removing the oxide material and nitride material at a removal rate ratio of the oxide material to the nitride material between about 10:1 or greater.
Another aspect of the invention provides a system for processing substrates, including a platen adapted for polishing the substrate with polishing media and a computer based controller configured to cause the system to position a substrate having at least first and second dielectric materials disposed thereon on a polishing platen having polishing media disposed thereon, to deliver an abrasive free polishing composition comprising one or more surfactants to a substrate surface, to polish the substrate surface with the polishing media, and to remove the first dielectric material at a higher removal rate than the second dielectric material from a substrate surface.
Another aspect of the invention provides a method of processing a substrate including contacting a substrate having at least one dielectric material and one conductive material disposed thereon with a polishing platen having polishing media disposed thereon, providing an abrasive free polishing composition comprising one or more surfactants to the substrate, and removing the dielectric material at a higher removal rate than the conductive material.